A Configurable and Efficient Memory Hierarchy for Neural Network Hardware Accelerator

by Oliver Bause, Paul Palomero Bernardo, and Oliver Bringmann
In MBMV 2024; 27. Workshop, pages 31–40, 2024.

Contribution to the Development of a Smart Video Capsule Endoscopy (VCE) System for Enhanced Gastrointestinal Diagnosis

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Abstract

Video Capsule Endoscopy (VCE) is a diagnostic tool for a minimal-invasive examination of the gastrointestinal tract. As part of an ongoing research project, we are developing a Smart VCE prototype that integrates AI-assisted image analysis, real-time sensor data processing, on-device decision making, and monitoring. To test and verify the prototype, we are simultaniously building a hardware-in-the-loop (HIL) setup.

Potential Topics

• Implementation of new hardware modules in SystemVerilog
• Extend the HIL setup
• Development and comparision of decision making approaches
• …

Requirements

• SystemVerilog
  • Successfully attended “ESES” or “MAES” (optional)
• C/C++
• Python
• Development of device driver
  • Successfully attended “PULPA” (optional)

HW-efficient Implementation of the Viterbi Algorithm for the Video Capsule Endoscopy

Master’s Thesis

Leveraging the Pico PIO API for Generalized Descriptions of State Machine-Based Interfaces

Master’s Thesis

HW-Development of a Minimal ML-based Image Processing Pipeline for Video Capsule Endoscopy

Master’s Thesis